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1 ? fn9073.5 ISL6406, isl6426 single synchronous buck pulse-width modulation (pwm) controller the ISL6406, isl6426 is an adjustable frequency, synchronous buck switching regulator optimized for generating lower voltages for the distributed dc-dc architectures. the ISL6406 offers an adjustable output voltage, while the isl6426 provides a fixed 1.8v output. designed to drive n-channel mosfets in synchronous buck topology, the ISL6406, isl6426 integrates the control, output adjustment and protection functions into a single package. the ISL6406, isl6426 provides simple, single feedback loop, voltage-mode control with fast transient response. the output voltage can be precisely regulated to as low as 0.8v. the error amplifier featur es a 15mhz gain-bandwidth product and 6v/ s slew rate which enables high converter bandwidth for fast transient performance. protection from overcurrent co nditions is provided by monitoring the r ds(on) of the upper mosfet to inhibit pwm operation appropriately. this approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. the wide programmable switching frequency range of 100khz to 700khz allows the use of small surface mount inductors and capacitors. the device also provides external frequency synchronization making it an ideal choice for dc-dc converter applications. features ? operates from 3.3v/5v input ? 0.8v to v in output range - 0.8v internal reference - 1.5% reference accuracy ? simple single-loop control design - voltage-mode pwm control ? fast transient response - high-bandwidth error amplifier ? lossless, programmable overcurrent protection - uses upper mosfet?s r ds(on) ? programmable switching frequency 100khz?700khz ? external frequency synchronization ? two device options available - ISL6406 . . . . . . . . . . . . . . . . adjustable output voltage - isl6426 . . . . . . . . . . . . . . . . . . . . . . fixed 1.8v output ? internal soft-start ? qfn package option - qfn compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - qfn near chip scale package footprint; improves pcb efficiency, thinner in profile ? pb-free packaging available - designated with ?z? suffix (refer to note) applications ? 3v/5v dc-dc converter modules ? distributed dc-dc 3.3v, 2.5v and 1.8v power architectures for dsp, logic, and memory ? power supplies for microprocessors -pcs - embedded controllers ? memory supplies ? personal computer peripherals data sheet july 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003-2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 pinouts ISL6406, isl6426 (soic/tssop) top view ISL6406, isl6426 (qfn) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 gnd lgate cpvout ocset ct1 ct2 sync/en rt ugate phase vcc cpgnd comp vout fb boot cpvout ocset ct1 ct2 lgate gnd ugate boot phase vcc cpgnd comp rt sync/en fb vout 1 3 4 15 16 14 13 2 12 10 9 11 6 578 ordering information part number temp. range ( o c) package pkg. dwg. # ISL6406cb 0 to 70 16 ld soic m16.15 ISL6406cbz (see note) 0 to 70 16 ld soic (pb-free) m16.15 ISL6406ib -40 to 85 16 ld soic m16.15 ISL6406ibz (see note) -40 to 85 16 ld soic (pb-free) m16.15 ISL6406cr 0 to 70 16 ld qfn l16.5x5b ISL6406crz (see note) 0 to 70 16 ld qfn (pb-free) l16.5x5b ISL6406ir -40 to 85 16 ld qfn l16.5x5b ISL6406irz (see note) -40 to 85 16 ld qfn (pb-free) l16.5x5b ISL6406cv 0 to 70 16 ld tssop m16.173 ISL6406cvz (see note) 0 to 70 16 ld tssop (pb-free) m16.173 ISL6406iv -40 to 85 16 ld tssop m16.173 ISL6406ivz (see note) -40 to 85 16 ld tssop (pb-free) m16.173 isl6426cb 0 to 70 16 ld soic m16.15 isl6426cbz (see note) 0 to 70 16 ld soic (pb-free) m16.15 isl6426ib -40 to 85 16 ld soic m16.15 isl6426ibz (see note) -40 to 85 16 ld soic (pb-free) m16.15 isl6426cr 0 to 70 16 ld qfn l16.5x5b isl6426crz (see note) 0 to 70 16 ld qfn (pb-free) l16.5x5b isl6426ir -40 to 85 16 ld qfn l16.5x5b isl6426irz (see note) -40 to 85 16 ld qfn (pb-free) l16.5x5b isl6426cv 0 to 70 16 ld tssop m16.173 isl6426cvz (see note) 0 to 70 16 ld tssop (pb-free) m16.173 isl6426iv -40 to 85 16 ld tssop m16.173 isl6426ivz (see note) -40 to 85 16 ld tssop (pb-free) m16.173 add ?-t? suffix to part number for tape and reel packaging. note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. ordering information part number temp. range ( o c) package pkg. dwg. # ISL6406, isl6426
3 functional block diagram + - + - + - oscillator inhibit pwm comparator error amp cpvout pwm gnd fb vout 0.8v oc comparator gate control logic boot ugate phase 20 a sync/en lgate softstart ocset reset (por) power-on + - vcc ct1 ct2 cpgnd pump charge rt sdwn sdwn comp ISL6406, isl6426
4 typical application sc hematic for 5v input typical application sc hematic for 3.3v input v out fb comp ugate phase boot gnd lgate ISL6406, isl6426 r fb r offset c i c f r f l out d boot c boot c in c hf c out ocset cpvout c bulk r ocset q 1 q 2 ct1 ct2 cpgnd vout vcc 5v 10% v in c dcpl r t rt sync/en vcc nc v out fb comp ugate phase boot gnd lgate ISL6406, isl6426 r fb r offset c i c f r f l out d boot c boot c in c pump c hf c out ocset cpvout c bulk r ocset q 1 q 2 ct1 ct2 cpgnd vout vcc 3.3v 10% v in c dcpl r t rt sync/en vcc ISL6406, isl6426
5 absolute maximum rati ngs thermal information supply voltage, vcc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . +15.0v upper driver supply voltage, v boot - v phase . . . . . . . . . . . +6.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.3v to vcc +0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions temperature range ISL6406, isl6426c . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c ISL6406, isl6426i . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3v 10% thermal resistance (typical) ja ( o c/w) jc ( o c/w) 16 lead soic (note 2) . . . . . . . . . . . . 70 n/a 16 lead tssop (note 2) . . . . . . . . . . . 90 n/a 16 lead qfn (notes 3, 4) . . . . . . . . . . 35 5 maximum junction temperature (plastic package) . -55 o c to 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. please refer to the typical appl ication schematics (page 3) for 3.3v / 5v input configuration. 2. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 3. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram and typical application schematic. v cc = +3.3v. typical values are at t a = 25 o c. parameter test conditions min typ max units v cc supply shutdown supply current sync/en = gnd - 20 50 a operating supply current (note 5) rt = 64.9k ? 7 9.8 11.5 ma reference voltage nominal reference voltage -0.8- v reference voltage tolerance -1.5 - 1.5 % t a = 0 o c to 70 o c -1.8 - 1.8 % t a = -40 o c to +85 o c -2.1 - 2.1 % error amplifier open loop voltage gain (note 6) - 82 - db gain-bandwidth product (note 6) 14 - - mhz slew rate (note 5) comp = 10pf 4.65 6.0 9.2 v/ s charge pump nominal charge pump output v cc = 3.3v, no load 4.8 5.1 5.5 v charge pump output regulation -5.0 - 5.0 % power-on reset rising cpvout por threshold t a = 0 o c to 70 o c 4.20 4.35 4.5 v t a = -40 o c to +85 o c 4.1 4.35 4.6 v cpvout por threshold hysteresis 0.3 0.5 0.9 v oscillator gate output frequency range rt = 200k ? 80 100 120 khz rt = 64.9k ? 250 300 340 khz rt = 26.1k ? 650 715 770 khz sawtooth amplitude peak-to-peak ? v osc 1.1 1.4 1.7 v ISL6406, isl6426
6 sync. frequency range (note 6) 1.1 times the natural switching frequency. 110 - 770 khz minimum sync pulse width (note 6) - 40 100 ns pwm maximum duty cycle -96- % gate driver output (note 6) upper gate source current v boot - v phase = 5v, v ugate = 4v - -1 - a upper gate sink current -1-a lower gate source current v vcc = 3.3v, v lgate = 4v - -1 - a lower gate sink current -2-a soft-start soft-start slew rate f = 300khz, t a = 0 o c to 70 o c 6.2 6.7 7.3 ms f = 300khz, t a = -40 o c to +85 o c 6.2 6.7 7.6 ms internal digital circuit clock count (soft-start time varies with frequency) - 2048 - clk cycles overcurrent ocset current source t a = 0 o c to 70 o c 182022 a t a = -40 o c to +85 o c 162023 a notes: 5. this is the v cc current consumed when the device is active but not switching. 6. guaranteed by design. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram and typical application schematic. v cc = +3.3v. typical values are at t a = 25 o c. (continued) parameter test conditions min typ max units typical performance curve figure 1. reference voltage vs temperature temperature (c) -40-30-20-10 0 1020304050607080 0.81 0.805 0.8 0.795 0.79 0.785 0.78 v ref (v) ISL6406, isl6426
7 pin descriptions cpvout - this pin represents th e output of the charge pump. the voltage at this pin is the bias voltage for the ic. connect a decoupling capacitor from this pin to ground. the value of the decoupling capacitor should be at least 10x the value of the charge pump capacitor. this pin may be tied to the bootstrap circuit as the source for creating the boot voltage. ct1 and ct2 - these pins are the connections for the external charge pump capacitor. a minimum of a 0.1 f ceramic capacitor is recommended for proper operation of the ic. ocset - connect a resistor (r ocset ) from this pin to the drain of the upper mosfet (v in ). r ocset , an internal 20 a current source (i ocset ), and the upper mosfet on- resistance (r ds(on) ) set the converter overcurrent (oc) trip point according to the following equation: an overcurrent trip cycles the soft-start function. vout - this pin provides the external switcher output voltage to the ic as feedba ck for the 1.8v fixed output voltage option. tie this pin to 1.8v for the isl6426 fixed 1.8v option. leave this pin open on the ISL6406 for the adjustable output voltage option. vcc - this pin provides bias supply for the ISL6406, isl6426. connect a well-coupled 3.3v supply to this pin. phase - connect this pin to the upper mosfet?s source. this pin is used to monitor the voltage drop across the upper mosfet for overcurrent protection. rt - connect an external resistor from this pin to ground for frequency selection. refer to rt vs frequency curve of figure 3. boot - this pin provides ground referenced bias voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage suitable to drive a logic-level n-channel mosfet. ugate - connect this pin to the upper mosfet?s gate. this pin provides the pwm-controll ed gate drive for the upper mosfet. this pin is also monitored by the adaptive shoot- through protection circuitry to determine when the upper mosfet has turned off. gnd - this pin represents the signal and power ground for the ic. tie this pin to the ground island/plane through the lowest impedance connection available. lgate - connect this pin to the lower mosfet?s gate. this pin provides the pwm-controlled gate drive for the lower mosfet. this pin is also monitored by the adaptive shoot- through protection circuitry to determine when the lower mosfet has turned off. comp and fb - comp and fb are the available external pins of the error amplifier. the fb pin is the inverting input of the internal error amplifier and the comp pin is the error amplifier output. these pins are used to compensate the control feedback loop of the converter. cpgnd - this pin represents the signal and power ground for the charge pump. tie this pin to the ground island/plane through the lowest impedance connection available. sync/en - this is a dual-function pin. to synchronize with an external clock, apply a clock with a frequency 1.1 times higher than the part?s natural frequency to this pin. the device may be disabled by tying this pin to ground. in this shutdown mode, all functions are disabled and the device will draw <50 a supply current. i peak i ocset () r ocset () r ds on () ------------------------------------------------------- - = ISL6406, isl6426
8 functional description initialization the ISL6406 automatically initializes upon receipt of power. special sequencing of the input supplies is not necessary. the power-on reset (por) functi on continually monitors the the output voltage of the charge pump. during por, the charge pump operates on a free running oscillator. once the por level is reached, the charge pump o scillator is syn ched to the pwm oscillator. the por function al so initiates the soft-start operation after the charge pump output voltage exceeds its por threshold. soft-start the por function initiates the digital soft-start sequence. the pwm error amplifier reference is clamped to a level proportional to the soft-start voltage. as the soft-start voltage slews up, the pwm comparator generates phase pulses of increasing width that charge th e output capacitor(s). this method provides a rapid and c ontrolled output voltage rise. the soft start sequence typically takes about 6.5ms. figure 2 shows the soft-start sequence for a typical application. at t0, the +3.3v vcc voltage starts to ramp. at time t1, the charge pump begins operation and the +5v cpvout ic bias voltage starts to ramp up. once the voltage on cpvout crosses the por threshold at time t2, the output begins the soft-start sequence. the triangle waveform from the pwm oscillator is compared to the rising error amplifier output voltage. as the error amplifier voltage increases, the pulse-width on the ugate pin increases to reach the steady-state duty cycle at time t3. frequency selection the ISL6406 offers adjustable frequency from 100khz to 700khz by changing external resistor connected at pin rt. figure 3 shows the typical rt vs frequency variation curve. shoot-through protection a shoot-through condition occurs when both the upper mosfet and lower mosfet are turned on simultaneously, effectively shorting the input voltage to ground. to protect the regulator from a shoot-t hrough condition, the ISL6406, isl6426 incorporates specialized circuitry which insures that the mosfets are not on simultaneously. the adaptive shoot-through pr otection utilized by the ISL6406, isl6426 looks at the lower gate drive pin, lgate, and the upper gate drive pin, ugate, to determine whether a mosfet is on or off. if the voltage from ugate or from lgate to gnd is less than 0.8v, then the respective mosfet is defined as being off and the other mosfet is turned on. this method of s hoot-through protection allows the regulator to sink or source current. since the voltage of the lowe r mosfet gate and the upper mosfet gate are being measured to determine the state of the mosfet, the designer is encouraged to consider the repercussions of introducing external components between the gate drivers and their res pective mosfet gates before actually implementing such measures. doing so may interfere with the shoo t-through protection. output voltage selection the output voltage can be programmed to any level between v in and the internal reference, 0.8v. an external resistor divider is used to scale the out put voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier, see figure 4. however, since the value of r1 affects the values of t he rest of the compensation components, it is advisable to keep its value less than 5k. r4 can be calculated based on the following equation: if the output voltage desired is 0.8v, simply route the output back to the fb pin through r1, but do not populate r4. figure 2. soft-start interval 0v time t2 t3 t0 cpvout (5v) vcc (3.3v) v out (2.50v) (1v/div) t1 figure 3. frequency vs rt 900 800 700 600 500 400 300 200 100 0 22 26.4 33.0 39 44.5 50 64.5 80 100 130 150 180 200 rt (k ? ) frequency (khz) r4 r1 () 0.8v () v out1 0.8v () ? ------------------------------------------ - = ISL6406, isl6426
9 when using the fixed 1.8v output isl6426 option, the internal resistor values are r1 = 3.5k ? and r2 = 2.8k ? , where r1 is connected from vout to fb and r2 is connected from fb to gnd. frequency synchronization and enable the external frequency synchronization and enable functions are combined in sync/en pin. this pin is ttl compatible for vcc = 3.3v or 5v. the device is disabled if the input to this pin is ttl low for more than 40 s (typ.); it is enabled if the input is ttl high without delay. the sync/en pin is monitored by the internal timer. the timer allows sync pulses (ttl low level) to pass through, as long as the pulses are shorter than 22 s. the minimum sync pulse width is 40ns (typ.). the oscillator can sync to an external frequency of between 1.0 times and 2.0 times the free-running frequency. loop acquisition time is about 200 clock cycles. the timing resistor (rt) is always re quired, regardless of whether sync pulses are being used or not. overcurrent protection the overcurrent function prot ects the converter from a shorted output by using the upper mosfet on-resistance, r ds(on) , to monitor the current. this method enhances the converter?s efficiency and reduces cost by eliminating a current sensing resistor. the over current function cycles the soft-start function in a hiccup mode to provide fault protection. a resistor (r ocset ) programs the over current trip level (see typical application diagrams). an internal 20a (typical) current sink develops a voltage across r ocset that is referenced to v in . when the voltage across the upper mosfet (also referenced to v in ) exceeds the voltage across r ocset , the over current function initiates a soft-start sequence. figure 5 illustrates the protection feature responding to an overcurrent event. at time t0 , an overcurrent condition is sensed across the upper mosfet. as a result, the regulator is quickly shutdown and the internal soft-start function begins producing soft-start ramps. the delay interval seen by the output is equivalent to three soft-start cycles. the fourth internal soft-start cycle initiates a normal soft-start ramp of the output, at time t1. the output is brought back into regulation by time t2, as long as the overcurrent event has cleared. had the cause of the over current still been present after the delay interval, the over current co ndition would be sensed and the regulator would be shut down again for another delay interval of three soft-start cycles. the resulting hiccup mode style of protection would continue to repeat indefinitely. the overcurrent function will trip at a peak inductor current (i peak) determined by: where i ocset is the internal ocset current source (20a typical). the oc trip point varies mainly due to the mosfet r ds(on) variations. to avoid overcurrent tripping in the normal operating load range, find the r ocset resistor from the equation above with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine i peak for, i peak > i out(max) + (di/2) where di is the output inductor ripple current. figure 4. output voltage selection + r1 c out +3.3v v out r4 l out ISL6406, c4 q1 fb ugate vcc boot comp d1 r2 c2 c1 r3 c3 phase lgate q2 cpvout vin isl6426 figure 5. overcurrent protection response 0v time v out (2.5v) t1 t0 t2 internal soft-start function delay interval i peak i ocset () r ocset () r ds on () ------------------------------------------------------- - = ISL6406, isl6426
10 for an equation for the ripple current see the section under component selection guidelines titled output inductor selection . a small ceramic capacito r should be placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switchi ng noise on the input voltage. current sinking the ISL6406, isl6426 incorporates a mosfet shoot- through protection method which allows a converter to sink current as well as source current. care should be exercised when designing a converter with the ISL6406, isl6426 when it is known that the conver ter may sink current. when the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. this means that the converter is boosting curre nt into the input rail of the regulator. if there is nowhere for this current to go, such as to other distributed loads on the rail or through a voltage limiting protection device, the capacitance on this rail will absorb the current. this situation will allow the voltage level of the input rail to increase. if the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of any components attached to the input rail, then those components may experience an irreversible failure or experience stress that may shorten their lifespan. ensuring that there is a path for the current to flow other than the capacitance on the rail will prevent this failure mode. application guidelines layout considerations layout is very important in high frequency switching converter design. with power devices switching, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, ra diate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimizes the voltage spikes in the converters. as an example, consider the turn-off transition of the pwm mosfet. prior to turn-off, the mosfet is carryi ng the full load current. during turn-off, current stops flowing in the mosfet and is picked up by the lower mosfet. any parasitic inductance in the switched current path generates a la rge voltage spike during the switching interval. careful compon ent selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. there are two sets of crit ical components in a dc-dc converter using the ISL6406, isl6426. the switching components are the most critical because they switch large amounts of energy, and theref ore tend to generate large amounts of noise. next are the small signal components, which connect to sensitive nodes or supply critical bypass current and signal coupling. a multi-layer printed circuit board is recommended. figure 6 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminals to the output inductor short. the power plane should support the input power and output power nodes. use copper-filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the gate pins to the mosfet gates should be kept short and wide enough to easily handle the 1a of drive current. the switching components should be placed close to the ISL6406, isl6426 first. minimize the length of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain and islands as possible. position the output inductor and output capacitors between the upper and lower mosfets and the load. v out island on power plane layer island on circuit plane layer l out c out c in +3.3v v in key comp ISL6406 ugate r4 r 2 c bp fb gnd cpvout figure 6. printed circuit board power planes and islands r 1 boot c 2 via connection to ground plane load q1 c boot phase d1 r 3 c 3 c 1 q2 lgate phase vcc c vcc ISL6406, isl6426
11 the critical small signal components include any bypass capacitors, feedback components, and compensation components. position the bypass capacitor, c bp , close to the vcc pin with a via directly to the ground plane. place the pwm converter compensation components close to the fb and comp pins. the feedback resistors for both regulators should also be locate d as close as possible to the relevant fb pin with vias tied straight to the ground plane as required. feedback compensation figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier (error amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with a peak amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l and c o ).the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to- peak oscillator voltage, v osc . modulator break frequency equations the compensation network consists of the error amplifier (internal to the ISL6406, isl6426) and the impedance networks z in and z fb .the goal of the compensation network is to provide a closed-loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 degrees. the equations below relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 and c 3 ) in figure 7. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r 2 /r 1 ) for desired converter bandwidth. 2. place first zero below filter?s double pole (~75% f lc ). 3. place second zero at filter?s double pole. 4. place first pole at the esr zero. 5. place second pole at half the switching frequency. 6. check gain against error amplifier?s open-loop gain. 7. estimate phase margin?repeat if necessary. when using the fixed 1.8v output isl6426 option, the internal resistor values are r1 = 3.5k ? and r2 = 2.8k ? , where r1 is connected from vout to fb and r2 is connected from fb to gnd. compensation break frequency equations figure 8 shows an asymptotic plot of the dc-dc converter?s gain vs frequency. the actual modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 8. using the above guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the graph of figure 8 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45 degrees. include worst-case component variations when determining phase margin. figure 7. voltage-mode buck converter compensation design v out reference l o c o esr v in ? v osc error amp pwm driver (parasitic) z fb + - reference r 1 r 3 r 2 c 3 c 1 c 2 comp v out fb z fb ISL6406, isl6426 z in comparator driver detailed compensation components phase v e/a + - + - z in osc f lc 1 2 l o c o ----------------------------- = f esr 1 2 esr () c o () ---------------------------------------- = ISL6406, isl6426
12 component selection guidelines charge pump capacitor selection a capacitor across pins ct1 and ct2 is required to create the proper bias voltage for the ISL6406, isl6426 when operating the ic from 3.3v. selecting the proper capacitance value is important so that th e bias current draw and the current required by the mosfet gates do not overburden the capacitor. a conservative approach is presented in the following equation. output capacitor selection an output capacitor is required to filter the output and supply the load transient current. th e filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern digital ics can produce high transient load slew rates. high-frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high-frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirem ents. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr valu e is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolyt ic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. th e inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the ISL6406, isl6426 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic figure 8. asymptotic bode plot of converter gain 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain modulator gain loop gain 20 v in v osc --------------- - ?? ?? ?? log 20 r2 r1 ------- - ?? ?? log c pump i bias i gate + v cc f s () -------------------------------------- 1 . 5 () = ? i= v in - v out f s x l v out v in ? v out = ? i x esr x t rise = l x i tran v in - v out t fall = l x i tran v out ISL6406, isl6426
13 capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q 1 turns on. place the small ceramic capacitors phys ically close to the mosfets and between the drain of q 1 and the source of q 2 . the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rm s current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. the maximum rms current required by the regulator may be closely approximated thro ugh the following equation: for a through hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge cu rrent rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge curre nt tested. mosfet selection/considerations the ISL6406, isl6426 requires two n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor. the switching losses seen when sourcing current will be different from the switching losses seen when sinking current. when sourcing current, the upper mosfet realizes most of the switching losses. the lower switch realizes most of the switching losses when the conver ter is sinking current (see equations on next page). these equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower mosfet?s body diode. the gate-charge losses are dissipated by the ISL6406, isl6426 and don't heat the mosfets. however, large gate- charge increases the switching interval, t sw which increases the mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. given the reduced available gate bias voltage (5v), logic- level or sub-logic-level transistors should be used for both n- mosfets. caution should be exercised with devices exhibiting very low v gs(on) characteristics. the shoot- through protection present aboard the ISL6406, isl6426 may be circumvented by these mo sfets if they have large parasitic impedances and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. bootstrap component selection external bootstrap components, a diode and capacitor, are required to provide sufficient gate enhancement to the upper mosfet. the internal mosfet gate driver is supplied by the external bootstrap circuitry as shown in figure 9. the boot capacitor, c boot , develops a floating supply voltage referenced to the phase pin. th is supply is refreshed each cycle, when d boot conducts, to a voltage of cpvout less the boot diode drop, v d , plus the voltage rise across q lower . i rms max v out v in ------------- - i out max 2 1 12 ------ v in v out ? lf s ---------------------------- - v out v in ------------- - ?? ?? 2 + ?? ?? = p lower = io 2 x r ds(on) x (1 - d) where: d is the duty cycle = v out / v in , t sw is the combined switch on and off time, and f s is the switching frequency. losses while sourcing current losses while sinking current p lower io 2 r ds on () 1d ? () 1 2 -- - io ? v in t sw f s + = p upper io 2 r ds on () d 1 2 -- - io ? v in t sw f s + = p upper = io 2 x r ds(on) x d ISL6406 gnd lgate ugate phase boot v in note: note: v g-s a v cc c boot d boot q upper q lower + - figure 9. upper gate drive bootstrap v g-s a v cc -v d + v d - cpvout isl6426 ISL6406, isl6426
14 just after the pwm switching cycle begins and the charge transfer from the bootstrap capacitor to the gate capacitance is complete, the voltage on the bootstrap capacitor is at its lowest point during the switching cycle. the charge lost on the bootstrap capacitor will be equal to the charge transferred to the equivalent gate-source capacitance of the upper mosfet as shown: where q gate is the maximum total gate charge of the upper mosfet, c boot is the bootstrap capacitance, v boot1 is the bootstrap voltage immediately before turn-on, and v boot2 is the bootstrap voltage immediately after turn-on. the bootstrap capacitor begins its refresh cycle when the gate drive begins to turn-off the upper mosfet. a refresh cycle ends when the upper mosfet is turned on again, which varies depending on the switching frequency and duty cycle. the minimum bootstrap capacitance can be calculated by rearranging the previous equation and solving for c boot . typical gate charge values for mosfets considered in these types of applications range from 20 to 100nc. since the voltage drop across q lower is negligible, v boot1 is simply v cpvout - v d . a schottky diode is recommended to minimize the voltage drop across the bootstrap capacitor during the on-time of the upper mosfet. initial calculations with v boot2 no less than 4v will quickly help narrow the bootstrap capacitor range. for example, consider an upper mosfet is chosen with a maximum gate charge, q g , of 100nc. limiting the voltage drop across the bootstrap capacitor to 1v results in a value of no less than 0.1 f. the tolerance of the ceramic capacitor should also be considered when selecting the final bootstrap capacitance value. a fast recovery diode is recommended when selecting a bootstrap diode to reduce the im pact of reverse recovery charge loss. otherwise, the recovery charge, q rr , would have to be added to the gate charge of the mosfet and taken into consideration when calculating the minimum bootstrap capacitance. q gate c boot v boot1 v boot2 ? () = c boot q gate v boot1 v ? boot2 ---------------------------------------------------- - = ISL6406, isl6426
15 ISL6406, isl6426 dc-dc conver ter application circuit the circuit below shows the device as it is configured on the ISL6406, isl6426 evaluation board. detailed information on the circuit, including a complete bill-of-materials and circuit board description, can be found in application note an1031. 2.5v @ 5a fb comp ugate phase boot gnd lgate r 3 r 5 c 10 c 11 r 2 l 1 d 1 c 7 c 1a-b c 4 c 6 c 8a-c ocset cpvout c 3 r 1 q 1 ct1 ct2 cpgnd sync/en vcc 3.3v c 5 c 2 c 9 r 4 gnd u 1 gnd 16 1 2 3 5 6 11 4 8 12 13 14 15 r 7 p 1 p 2 p 3 tp 1 p 5 tp 3 9 rt vout r 5 7 10 p 4 gnd p 6 note: remove r3, r4, c9, and r5 from the board and close jp1 for isl6426 evaluation. jp1 ISL6406 isl6426 ISL6406, isl6426
16 ISL6406, isl6426 ISL6406, isl6426 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optiona l. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are sh own for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 02/02
17 ISL6406, isl6426 thin shrink small outline plastic packages (tssop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ab, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optiona l. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are sh own for reference only. 9. dimension ?b? does not inclu de dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. (angles in degrees) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 0.05(0.002) m16.173 16 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.043 - 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - d 0.193 0.201 4.90 5.10 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.020 0.028 0.50 0.70 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 2/02
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6406, isl6426 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.5x5b 16 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhb issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.28 0.33 0.40 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7, 8 e 0.80 bsc - k0.25--- l 0.35 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p--0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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